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-- Company: 
-- Engineer: 
-- 
-- Create Date: 2022/08/03 21:41:04
-- Design Name: 
-- Module Name: ENCODER8_3 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY ENCODER8_3 IS
  PORT (
    A : IN STD_LOGIC;
    B : IN STD_LOGIC;
    C : IN STD_LOGIC;
    D : IN STD_LOGIC;
    E : IN STD_LOGIC;
    F : IN STD_LOGIC;
    G : IN STD_LOGIC;
    H : IN STD_LOGIC;
    Y0 : OUT STD_LOGIC;
    Y1 : OUT STD_LOGIC;
    Y2 : OUT STD_LOGIC);
END ENCODER8_3;

ARCHITECTURE Behavioral OF ENCODER8_3 IS
  SIGNAL SY : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
  SY(2 DOWNTO 0) <= "111" WHEN H = '1' ELSE
                    "110" WHEN G = '1' ELSE
                    "101" WHEN F = '1' ELSE
                    "100" WHEN E = '1' ELSE
                    "011" WHEN D = '1' ELSE
                    "010" WHEN C = '1' ELSE
                    "001" WHEN B = '1' ELSE
                    "000" WHEN A = '1' ELSE
                    "XXX";
  Y0 <= SY(0);
  Y1 <= SY(1);
  Y2 <= SY(2);
END Behavioral;